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slas361c ? january 2002 ? revised december 2003 1 post office box 655303 ? dallas, texas 75265 low supply voltage range 1.8 v ? 3.6 v ultralow-power consumption: ? active mode: 200 a at 1 mhz, 2.2 v ? standby mode: 0.7 a ? off mode (ram retention): 0.1 a five power saving modes wake-up from standby mode in less than 6 s 16-bit risc architecture, 125 ns instruction cycle time basic clock module configurations: ? various internal resistors ? single external resistor ? 32-khz crystal ? high frequency crystal ? resonator ? external clock source 16-bit timer_a with three capture/compare registers 10-bit, 200-ksps a/d converter with internal reference, sample-and-hold, autoscan, and data transfer controller serial communication interface (usart0) with software-selectable asynchronous uart or synchronous spi (msp430x12x2 only) serial onboard programming, no external programming voltage needed programmable code protection by security fuse supply voltage brownout protection msp430x11x2 family members include: msp430f1122: 4kb + 256b flash memory 256b ram msp430f1132: 8kb + 256b flash memory 256b ram available in 20-pin plastic sowb, 20-pin plastic tssop and 32-pin qfn packages msp430x12x2 family members include: msp430f1222: 4kb + 256b flash memory 256b ram msp430f1232: 8kb + 256b flash memory 256b ram available in 28-pin plastic sowb, 28-pin plastic tssop, and 32-pin qfn packages for complete module descriptions, see the msp430x1xx family user?s guide , literature number slau049 description the texas instruments msp430 family of ultralow-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. the architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. the device features a powerful 16-bit risc cpu, 16-bit registers, and constant generators that attribute to maximum code ef ficiency. the digitally controlled oscillator (dco) allows wake-up from low-power modes to active mode in less than 6 s. the msp430x11x2 and msp430x12x2 series are ultralow-power mixed signal microcontrollers with a built-in 16-bit timer, 10-bit a/d converter with integrated reference and data transfer controller (dtc) and fourteen or twenty-two i/o pins. in addition, the msp430x12x2 series microcontrollers have built-in communication capability using asynchronous (uart) and synchronous (spi) protocols. digital signal processing with the 16-bit risc performance enables effective system solutions such as glass breakage detection with signal analysis (including wave digital filter algorithm). another area of application is in stand-alone rf sensors. please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. copyright ? 2002 ? 2003, texas instruments incorporated
slas361c ? january 2002 ? revised december 2003 2 post office box 655303 ? dallas, texas 75265 available options packaged devices t a plastic 20-pin sowb (dw) plastic 20-pin tssop (pw) plastic 28-pin sowb (dw) plastic 28-pin tssop (pw) plastic 32-pin qfn (rhb) ?40 c to 85 c MSP430F1122IDW msp430f1122ipw msp430f1222idw msp430f1222ipw msp430f1122irhb msp430f1132irhb ?40 c to 85 c MSP430F1122IDW msp430f1132idw msp430f1122ipw msp430f1132ipw msp430f1222idw msp430f1232idw msp430f1222ipw msp430f1232ipw msp430f1132irhb msp430f1222irhb msp430f1232irhb pin designation, msp430x11x2 (see note) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 test v cc p2.5/r osc v ss xout xin rst /nmi p2.0/aclk/a0 p2.1/inclk/a1 p2.2/ta0/a2 p1.7/ta2/tdo/tdi p1.6/ta1/tdi/tclk p1.5/ta0/tms p1.4/smclk/tck p1.3/ta2 p1.2/ta1 p1.1/ta0 p1.0/taclk/adc10clk p2.4/ta2/a4/v ref+ /v eref+ p2.3/ta1/a3/v ref? /v eref? dw or pw package (top view) rhb package (top view) xin p2.5/r osc nc nc rst /nmi v cc p2.0/aclk/a0 test p2.1/inclk/a1 p1.7/ta2/tdo/tdi xout p1.6/ta1/tdi/tclk p1.1/ta0 p1.0/taclk/adc10clk nc p2.4/ta2/a4/v ref+ /v eref+ p2.3/ta1/a3/v ref? /v eref? p1.2/ta1 note: it is recommended that all nc pins be connected to v ss to avoid floating nodes, otherwise increased current consumption may occur. power pad not internally connected. 1 10 11 12 13 27 28 29 p1.5/ta0/tms 2 5 7 6 3 4 14 30 31 v ss p1.3/ta2 8 24 23 20 18 19 22 21 17 26 15 p2.2/ta0/a2 nc p1.4/smclk/tck nc nc nc nc nc nc nc nc
slas361c ? january 2002 ? revised december 2003 3 post office box 655303 ? dallas, texas 75265 pin designation, msp430x12x2 (see note) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 dw or pw package (top view) test v cc p2.5/r osc v ss xout xin rst /nmi p2.0/aclk/a0 p2.1/inclk/a1 p2.2/ta0/a2 p3.0/ste0/a5 p3.1/simo0 p3.2/somi0 p3.3/uclk0 p1.7/ta2/tdo/tdi p1.6/ta1/tdi/tclk p1.5/ta0/tms p1.4/smclk/tck p1.3/ta2 p1.2/ta1 p1.1/ta0 p1.0/taclk/adc10clk p2.4/ta2/a4/v ref+ /v eref+ p2.3/ta1/a3/v ref? /v eref? p3.7/a7 p3.6/a6 p3.5/urxd0 p3.4/utxd0 rhb package (top view) xin p2.5/r osc nc nc rst /nmi v cc p2.0/aclk/a0 test p2.1/inclk/a1 p1.7/ta2/tdo/tdi xout p1.6/ta1/tdi/tclk p1.1/ta0 p1.0/taclk/adc10clk nc p2.4/ta2/a4/v ref+ /v eref+ p2.3/ta1/a3/v ref? /v eref? p1.2/ta1 note: it is recommended that all nc pins be connected to v ss to avoid floating nodes, otherwise increased current consumption may occur. power pad not internally connected. 1 10 11 12 13 27 28 29 p3.0/ste0/a5 p3.1/simo0 p3.2/somi0 p3.3/uclk0 p3.4/utxd0 p3.5/urxd0 p3.6/a6 p1.5/ta0/tms 2 5 7 6 3 4 14 30 31 v ss p1.3/ta2 8 24 23 20 18 19 22 21 17 26 15 p2.2/ta0/a2 nc p3.7/a7 p1.4/smclk/tck
slas361c ? january 2002 ? revised december 2003 4 post office box 655303 ? dallas, texas 75265 functional block diagram, msp430x11x2 oscillator aclk smclk cpu incl. 16 reg. bus conv mcb xin xout p2 mdb, 16 bit mab, 16 bit mclk mab, 4 bit v cc v ss rst /nmi system clock r osc p1 8kb flash 4kb flash 256b ram adc10 10-bit autoscan dtc watchdog timer 15/16-bit timer_a3 3 cc reg i/o port 1 8 i/os, with interrupt capability i/o port 2 6 i/os, with interrupt capability por/ brownout mdb, 8 bit mdb, 16-bit mab, 16-bit jtag test test jtag emulation module 8 6 functional block diagram, msp430x12x2 oscillator aclk smclk cpu incl. 16 reg. bus conv mcb xin xout p3 p2 mdb, 16 bit mab, 16 bit mclk mab, 4 bit v cc v ss rst /nmi system clock r osc p1 8kb flash 4kb flash 256b ram adc10 10-bit autoscan dtc watchdog timer 15/16-bit timer_a3 3 cc reg i/o port 1 8 i/os, with interrupt capability i/o port 2 6 i/os, with interrupt capability por/ brownout usart0 uart mode spi mode i/o port 3 8 i/os mdb, 8 bit mdb, 16-bit mab, 16-bit jtag test test jtag emulation module 8 6 8
slas361c ? january 2002 ? revised december 2003 5 post office box 655303 ? dallas, texas 75265 terminal functions, msp430x11x2 terminal terminal i/o description name dw & pw rhb i/o description name dw & pw rhb i/o description p1.0/taclk/ adc10clk 13 21 i/o general-purpose digital i/o pin/timer_a, clock signal taclk input/conversion clock?10-bit adc p1.1/ta0 14 22 i/o general-purpose digital i/o pin/timer_a, capture: cci0a input, compare: out0 output/bsl transmit p1.2/ta1 15 23 i/o general-purpose digital i/o pin/timer_a, capture: cci1a input, compare: out1 output p1.3/ta2 16 24 i/o general-purpose digital i/o pin/timer_a, capture: cci2a input, compare: out2 output p1.4/smclk/tck 17 25 i/o general-purpose digital i/o pin/smclk signal output/test clock, input terminal for device programming and test p1.5/ta0/tms 18 26 i/o general-purpose digital i/o pin/timer_a, compare: out0 output/test mode select, input terminal for device programming and test p1.6/ta1/tdi/tclk 19 27 i/o general-purpose digital i/o pin/timer_a, compare: out1 output/test data input terminal or test clock input p1.7/ta2/tdo/tdi ? 20 28 i/o general-purpose digital i/o pin/timer_a, compare: out2 output/test data output terminal or data input during programming p2.0/aclk/a0 8 6 i/o general-purpose digital i/o pin/aclk output/analog input to 10-bit adc input a0 p2.1/inclk/a1 9 7 i/o general-purpose digital i/o pin/timer_a, clock signal at inclk/analog input to 10-bit adc input a1 p2.2/ta0/a2 10 8 i/o general-purpose digital i/o pin/timer_a, capture: cci0b input, compare: out0 output/analog input to 10-bit adc input a2/bsl receive p2.3/ta1/a3/v ref? / v eref? 11 18 i/o general-purpose digital i/o pin/timer_a, capture: cci1b input, compare: out1 output/analog input to 10-bit adc input a3/negative reference voltage terminal. p2.4/ta2/a4/v ref+ / v eref+ 12 19 i/o general-purpose digital i/o pin/timer_a, compare: out2 output/analog input to 10-bit adc input a4/i/o of positive reference voltage terminal p2.5/r osc 3 32 i/o general-purpose digital i/o pin/input for external resistor that defines the dco nominal frequency rst /nmi 7 5 i reset or nonmaskable interrupt input test 1 29 i selects test mode for jtag pins on p1.x v cc 2 30 supply voltage v ss 4 1 ground reference xin 6 3 i input terminal of crystal oscillator xout 5 2 o output terminal of crystal oscillator nc na 4,9-16, 17,20,31 no connect. recommended connection to v ss to avoid floating nodes, otherwise increased current consumption may occur. ? tdo or tdi is selected via jtag instruction.
slas361c ? january 2002 ? revised december 2003 6 post office box 655303 ? dallas, texas 75265 terminal functions, msp430x12x2 terminal terminal i/o description name dw & pw rhb i/o description name dw & pw rhb i/o description p1.0/taclk/ adc10clk 21 21 i/o general-purpose digital i/o pin/timer_a, clock signal taclk input/conversion clock?10-bit adc p1.1/ta0 22 22 i/o general-purpose digital i/o pin/timer_a, capture: cci0a input, compare: out0 output/bsl transmit p1.2/ta1 23 23 i/o general-purpose digital i/o pin/timer_a, capture: cci1a input, compare: out1 output p1.3/ta2 24 24 i/o general-purpose digital i/o pin/timer_a, capture: cci2a input, compare: out2 output p1.4/smclk/tck 25 25 i/o general-purpose digital i/o pin/smclk signal output/test clock, input terminal for device programming and test p1.5/ta0/tms 26 26 i/o general-purpose digital i/o pin/timer_a, compare: out0 output/test mode select, input terminal for device programming and test p1.6/ta1/tdi/tclk 27 27 i/o general-purpose digital i/o pin/timer_a, compare: out1 output/test data input terminal or test clock input p1.7/ta2/tdo/tdi ? 28 28 i/o general-purpose digital i/o pin/timer_a, compare: out2 output/test data output terminal or data input during programming p2.0/aclk/a0 8 6 i/o general-purpose digital i/o pin/aclk output/analog input to 10-bit adc input a0 p2.1/inclk/a1 9 7 i/o general-purpose digital i/o pin/timer_a, clock signal at inclk/analog input to 10-bit adc input a1 p2.2/ta0/a2 10 8 i/o general-purpose digital i/o pin/timer_a, capture: cci0b input, compare: out0 output/analog input to 10-bit adc input a2/bsl receive p2.3/ta1/a3/v ref? / v eref? 19 18 i/o general-purpose digital i/o pin/timer_a, capture: cci1b input, compare: out1 output/analog input to 10-bit adc input a3/negative reference voltage terminal. p2.4/ta2/a4/v ref+ / v eref+ 20 19 i/o general-purpose digital i/o pin/timer_a, compare: out2 output/analog input to 10-bit adc input a4/i/o of positive reference voltage terminal p2.5/r osc 3 32 i/o general-purpose digital i/o pin/input for external resistor that defines the dco nominal frequency p3.0/ste0/a5 11 9 i/o general-purpose digital i/o pin/slave transmit enable?usart0/spi mode/analog input to 10-bit adc input a5 p3.1/simo0 12 10 i/o general-purpose digital i/o pin/slave in/master out of usart0/spi mode p3.2/somi0 13 11 i/o general-purpose digital i/o pin/slave out/master in of usart0/spi mode p3.3/uclk0 14 12 i/o general-purpose digital i/o pin/external clock input?usart0/uart or spi mode, clock output?usart0/spi mode clock input p3.4/utxd0 15 13 i/o general-purpose digital i/o pin/transmit data out?usart0/uart mode p3.5/urxd0 16 14 i/o general-purpose digital i/o pin/receive data in?usart0/uart mode p3.6/a6 17 15 i/o general-purpose digital i/o pin/analog input to 10-bit adc input a6 p3.7/a7 18 16 i/o general-purpose digital i/o pin/analog input to 10-bit adc input a7 rst /nmi 7 5 i reset or nonmaskable interrupt input test 1 29 i selects test mode for jtag pins on p1.x v cc 2 30 supply voltage v ss 4 1 ground reference xin 6 3 i input terminal of crystal oscillator xout 5 2 o output terminal of crystal oscillator nc na 4,17, 20,31 no connect. recommended connection to v ss to avoid floating nodes, otherwise increased current consumption may occur. ? tdo or tdi is selected via jtag instruction.
general-purpose register program counter stack pointer status register constant generator general-purpose register general-purpose register general-purpose register pc/r0 sp/r1 sr/cg1/r2 cg2/r3 r4 r5 r12 r13 general-purpose register general-purpose register r6 r7 general-purpose register general-purpose register r8 r9 general-purpose register general-purpose register r10 r11 general-purpose register general-purpose register r14 r15 slas361c ? january 2002 ? revised december 2003 7 post office box 655303 ? dallas, texas 75265 short-form description cpu the msp430 cpu has a 16-bit risc architecture that is highly transparent to the application. all operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. the cpu is integrated with 16 registers that provide reduced instruction execution time. the register-to-register operation execution time is one cycle of the cpu clock. four of the registers, r0 to r3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. the remaining registers are general-purpose registers. peripherals are connected to the cpu using data, address, and control buses, and can be handled with all instructions. instruction set the instruction set consists of 51 instructions with three formats and seven address modes. each instruction can operate on word and byte data. table 1 shows examples of the three types of instruction formats; the address modes are listed in table 2. table 1. instruction word formats dual operands, source-destination e.g. add r4,r5 r4 + r5 ???> r5 single operands, destination only e.g. call r8 pc ??>(tos), r8??> pc relative jump, un/conditional e.g. jne jump-on-equal bit = 0 table 2. address mode descriptions address mode s d syntax example operation register mov rs,rd mov r10,r11 r10 ??> r11 indexed mov x(rn),y(rm) mov 2(r5),6(r6) m(2+r5)??> m(6+r6) symbolic (pc relative) mov ede,toni m(ede) ??> m(toni) absolute mov &mem,&tcdat m(mem) ??> m(tcdat) indirect mov @rn,y(rm) mov @r10,tab(r6) m(r10) ??> m(tab+r6) indirect autoincrement mov @rn+,rm mov @r10+,r11 m(r10) ??> r11 r10 + 2??> r10 immediate mov #x,toni mov #45,toni #45 ??> m(toni) note: s = source d = destination
slas361c ? january 2002 ? revised december 2003 8 post office box 655303 ? dallas, texas 75265 operating modes the msp430 has one active mode and five software selectable low-power modes of operation. an interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. the following six operating modes can be configured by software: active mode am; ? all clocks are active low-power mode 0 (lpm0); ? cpu is disabled aclk and smclk remain active. mclk is disabled low-power mode 1 (lpm1); ? cpu is disabled aclk and smclk remain active. mclk is disabled dco?s dc-generator is disabled if dco not used in active mode low-power mode 2 (lpm2); ? cpu is disabled mclk and smclk are disabled dco?s dc-generator remains enabled aclk remains active low-power mode 3 (lpm3); ? cpu is disabled mclk and smclk are disabled dco?s dc-generator is disabled aclk remains active low-power mode 4 (lpm4); ? cpu is disabled aclk is disabled mclk and smclk are disabled dco?s dc-generator is disabled crystal oscillator is stopped
slas361c ? january 2002 ? revised december 2003 9 post office box 655303 ? dallas, texas 75265 interrupt vector addresses the interrupt vectors and the power-up starting address are located in the memory with an address range of 0ffffh-0ffe0h. the vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. interrupt source interrupt flag system interrupt word address priority power-up, external reset, watchdog wdtifg (see note1) keyv (see note 1) reset 0fffeh 15, highest nmi, oscillator fault, flash memory access violation nmiifg (see notes 1 and 4) ofifg (see notes 1 and 4) accvifg (see notes 1 and 4) (non)-maskable, (non)-maskable, (non)-maskable 0fffch 14 0fffah 13 0fff8h 12 0fff6h 11 watchdog timer wdtifg maskable 0fff4h 10 timer_a taccr0 ccifg (see note 2) maskable 0fff2h 9 timer_a taccr1 and taccr2 ccifgs, taifg (see notes 1 and 2) maskable 0fff0h 8 usart0 receive (see note 5) urxifg0 maskable 0ffeeh 7 usart0 transmit (see note 5) utxifg0 maskable 0ffech 6 adc10 adc10ifg maskable 0ffeah 5 0ffe8h 4 i/o port p2 (eight flags ? see note 3) p2ifg.0 to p2ifg.7 (see notes 1 and 2) maskable 0ffe6h 3 i/o port p1 (eight flags) p1ifg.0 to p1ifg.7 (see notes 1 and 2) maskable 0ffe4h 2 0ffe2h 1 0ffe0h 0, lowest notes: 1. multiple source flags 2. interrupt flags are located in the module 3. there are eight port p2 interrupt flags, but only six port p2 i/o pins (p2.0?5) are implemented on the ?11x2 and ?12x2 device s. 4. (non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable cannot. 5. usart0 is implemented in msp430x12x2 only.
slas361c ? january 2002 ? revised december 2003 10 post office box 655303 ? dallas, texas 75265 special function registers most interrupt and module ena ble bits are collected into the lowest address space. special function register bits that are not allocated to a functional purpose are not physically present in the device. simple software access is provided with this arrangement. interrupt enable 1 and 2 7654 0 ofie wdtie 32 1 rw-0 rw-0 rw-0 address 0h nmiie accvie rw-0 wdtie: watchdog ti mer interrupt enable. inactive if watchdog mode is selected. active if watchdog t imer is configured in interval timer mode. ofie: oscillator fault enable nmiie: (non)maskable interrupt enable accvie: flash access violation interrupt enable 7654 0 32 1 address 01h utxie0 urxie0 rw-0 rw-0 urxie0: usart0, uart, and spi receive-interrupt enable (msp430x12x2 devices only) utxie0: usart0, uart, and spi transmit-interrupt enable (msp430x12x2 devices only) interrupt flag register 1 and 2 7654 0 ofifg wdtifg 32 1 rw-0 rw-1 rw-0 address 02h nmiifg wdtifg: set on watchdog timer overflow (in watchdog mode) or security key violation. reset on v cc power-up or a reset condition at rst /nmi pin in reset mode. ofifg: flag set on oscillator fault nmiifg: set via rst /nmi-pin 7654 0 32 1 address 03h utxifg0 urxifg0 rw-0 rw-1 urxifg0: usart0, uart, and spi receive flag (msp430x12x2 devices only) utxifg0: usart0, uart, and spi transmit flag (msp430x12x2 devices only)
slas361c ? january 2002 ? revised december 2003 11 post office box 655303 ? dallas, texas 75265 module enable registers 1 and 2 7654 0 32 1 address 04h 7654 0 32 1 address 05h utxe0 urxe0 uspie0 rw-0 rw-0 urxe0: usart0, uart mode receive enable (msp430x12x2 devices only) utxe0: usart0, uart mode transmit enable (msp430x12x2 devices only) uspie0: usart0, spi mode transmit and receive enable (msp430x12x2 devices only) legend rw: rw-0: bit can be read and written. bit can be read and written. it is reset by puc sfr bit is not present in device. memory organization int. vector 8 kb flash segment0?15 256b ram 16b per. 8b per. sfr ffffh ffe0h ffdfh 02ffh 0200h 01ffh 0100h 00ffh 0010h 000fh 0000h msp430f1132 msp430f1232 e000h main memory 10ffh 2 128b flash segmenta,b information memory 1000h 1 kb boot rom 0c00h int. vector 4 kb flash segment0?7 256b ram 16b per. 8b per. sfr ffdfh f000h 02ffh 0200h 0100h 00ffh 0010h 000fh 0000h msp430f1122 msp430f1222 1 kb boot rom 2 128b flash segmenta,b 10ffh 1000h 01ffh 0c00h 0fffh ffffh ffe0h 0fffh
slas361c ? january 2002 ? revised december 2003 12 post office box 655303 ? dallas, texas 75265 bootstrap loader (bsl) the msp430 bootstrap loader (bsl) enables users to program the flash memory or ram using a uart serial interface. access to the msp430 memory via the bsl is protected by user-defined password. for complete description of the features of the bsl and its implementation, see the application report features of the msp430 bootstrap loader , literature number slaa089. bsl function msp430x11x2 dw & pw package (20 pins) msp430x12x2 dw & pw package (28 pins) msp430x11x2/12x2 rhb package (32 pins) data transmit 14 - p1.1 22 - p1.1 22 - p1.1 data receive 10 - p2.2 10 - p2.2 8 - p2.2 flash memory the flash memory can be programmed via the jtag port, the bootstrap loader, or in-system by the cpu. the cpu can perform single-byte and single-word writes to the flash memory. features of the flash memory include: flash memory has n segments of main memory and two segments of information memory (a and b) of 128 bytes each. each segment in main memory is 512 bytes in size. segments 0 to n may be erased in one step, or each segment may be individually erased. segments a and b can be erased individually, or as a group with segments 0?n. segments a and b are also called information memory. new devices may have some bytes programmed in the information memory (needed for test during manufacturing). the user should perform an erase of the information memory prior to the first use. segment0 w/ interrupt vectors 0ffffh 0fe00h information memory flash main memory segment1 segment2 segment3 segment4 segment14 segment15 segmenta segmentb 0fdffh 0fc00h 0fbffh 0fa00h 0f9ffh 0f800h 0f7ffh 0f600h 0e3ffh 0e200h 0e1ffh 0e000h 010ffh 01080h 0107fh 01000h note: all segments not implemented on all devices.
slas361c ? january 2002 ? revised december 2003 13 post office box 655303 ? dallas, texas 75265 peripherals peripherals are connected to the cpu through data, address, and control busses and can be handled using all instructions. for complete module descriptions, see the msp430x1xx family user ?s guide , literature number slau049. oscillator and system clock the clock system in the msp430x11x2 and msp430x12x2 devices is supported by the basic clock module that includes support for a 32768-hz watch crystal oscillator, an internal digitally-controlled oscillator (dco) and a high frequency crystal oscillator. the basic clock module is designed to meet the requirements of both low system cost and low-power consumption. the internal dco provides a fast turn-on clock source and stabilizes in less than 6 s. the basic clock module provides the following clock signals: auxiliary clock (aclk), sourced from a 32768-hz watch crystal or a high frequency crystal. main clock (mclk), the system clock used by the cpu. sub-main clock (smclk), the sub-system clock used by the peripheral modules. digital i/o there are 3 8-bit i/o ports implemented?ports p1, p2, and p3 (only six port p2 i/o signals are available on external pins; port p3 is implemented only on ?x12x2 devices): all individual i/o bits are independently programmable. any combination of input, output, and interrupt conditions is possible. edge-selectable interrupt input capability for all the eight bits of ports p1 and six bits of port p2. read/write access to port-control registers is supported by all instructions. note: six bits of port p2, p2.0 to p2.5, are available on external pins, but all control and data bits for port p2 are implemented. port p3 has no interrupt capability. port p3 is implemented in msp430x12x2 only. brownout the brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. watchdog timer the primary function of the watchdog timer (wdt) module is to perform a controlled system restart after a software problem occurs. if the selected time interval expires, a system reset is generated. if the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. usart0 (msp430x12x2 only) the msp430x12x2 devices have one hardware universal synchronous/asynchronous receive transmit (usart0) peripheral module that is used for serial data communication. the usart supports synchronous spi (3 or 4 pin) and asynchronous uar t communication protocols, using double-buffered transmit and receive channels. adc10 the adc10 module supports fast, 10-bit analog-to-digital conversions. the module implements a 10-bit sar core, sample select control, reference generator and data transfer controller, or dtc, for automatic conversion result handling allowing adc samples to be converted and stored without any cpu intervention.
slas361c ? january 2002 ? revised december 2003 14 post office box 655303 ? dallas, texas 75265 timer_a3 timer_a3 is a 16-bit timer/counter with three capture/compare registers. timer_a3 can support multiple capture/compares, pwm outputs, and interval timing. timer_a3 also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. timer_a3 signal connections input pin number output pin number dw and pw rhb device input signal module input name module block module output signal dw and pw rhb ?11x2 20-pin ?12x2 28-pin ?11x2/12x2 32-pin device input signal module input name module block module output signal ?11x2 20-pin ?12x2 28-pin ?11x2/12x2 32-pin 13 - p1.0 21 - p1.0 21 - p1.0 taclk taclk aclk aclk timer na smclk smclk timer na 9 - p2.1 9 - p2.1 7 - p2.1 inclk inclk 14 - p1.1 22 - p1.1 22 - p1.1 ta0 cci0a 14 - p1.1 22 - p1.1 22 - p1.1 10 - p2.2 10 - p2.2 8 - p2.2 ta0 cci0b ccr0 ta0 18 - p1.5 26 - p1.5 26 - p1.5 dv ss gnd ccr0 ta0 10 - p2.2 10 - p2.2 8 - p2.2 dv cc v cc adc10 internal 15 - p1.2 23 - p1.2 23 - p1.2 ta1 cci1a 15 - p1.2 23 - p1.2 23 - p1.2 11 - p2.3 19 - p2.3 18 - p2.3 ta1 cci1b ccr1 ta1 19 - p1.6 27 - p1.6 27 - p1.6 dv ss gnd ccr1 ta1 11 - p2.3 19 - p2.3 18 - p2.3 dv cc v cc adc10 internal 16 - p1.3 24 - p1.3 24 - p1.3 ta2 cci2a 16 - p1.3 24 - p1.3 24 - p1.3 aclk (internal) cci2b ccr2 ta2 20 - p1.7 28 - p1.7 28 - p1.7 dv ss gnd ccr2 ta2 12 - p2.4 20 - p2.4 19 - p2.4 dv cc v cc adc10 internal
slas361c ? january 2002 ? revised december 2003 15 post office box 655303 ? dallas, texas 75265 peripheral file map peripherals with word access adc10 adc data transfer start address adc memory adc control register 1 adc control register 0 adc10sa adc10mem adc10ctl1 adc10ctl0 1bch 1b4h 1b2h 1b0h adc control register 0 adc analog enable adc data transfer control register 1 adc data transfer control register 0 adc10ctl0 adc10ae adc10dtc1 adc10dtc0 1b0h 04ah 049h 048h timer_a reserved reserved reserved reserved capture/compare register capture/compare register capture/compare register timer_a register reserved reserved reserved reserved capture/compare control capture/compare control capture/compare control timer_a control timer_a interrupt vector taccr2 taccr1 taccr0 tar tacctl2 tacctl1 tacctl0 tactl taiv 017eh 017ch 017ah 0178h 0176h 0174h 0172h 0170h 016eh 016ch 016ah 0168h 0166h 0164h 0162h 0160h 012eh flash memory flash control 3 flash control 2 flash control 1 fctl3 fctl2 fctl1 012ch 012ah 0128h watchdog watchdog/timer control wdtctl 0120h peripherals with byte access usart0 (in msp430x12x2 only) transmit buffer receive buffer baud rate baud rate modulation control receive control transmit control usart control u0txbuf u0rxbuf u0br1 u0br0 u0mctl u0rctl u0tctl u0ctl 077h 076h 075h 074h 073h 072h 071h 070h basic clock basic clock sys. control2 basic clock sys. control1 dco clock freq. control bcsctl2 bcsctl1 dcoctl 058h 057h 056h port p2 port p2 selection port p2 interrupt enable port p2 interrupt edge select port p2 interrupt flag port p2 direction port p2 output port p2 input p2sel p2ie p2ies p2ifg p2dir p2out p2in 02eh 02dh 02ch 02bh 02ah 029h 028h port p1 port p1 selection port p1 interrupt enable port p1 interrupt edge select port p1 interrupt flag port p1 direction port p1 output port p1 input p1sel p1ie p1ies p1ifg p1dir p1out p1in 026h 025h 024h 023h 022h 021h 020h
slas361c ? january 2002 ? revised december 2003 16 post office box 655303 ? dallas, texas 75265 peripheral file map (continued) peripherals with byte access (continued) port p3 (in msp430x12x2 only) port p3 selection port p3 direction port p3 output port p3 input p3sel p3dir p3out p3in 01bh 01ah 019h 018h special function module enable2 module enable1 sfr interrupt flag2 sfr interrupt flag1 sfr interrupt enable2 sfr interrupt enable1 me2 me1 ifg2 ifg1 ie2 ie1 005h 004h 003h 002h 001h 000h absolute maximum ratings ? voltage applied at v cc to v ss ?0.3 v to 4.1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage applied to any pin (see note) ?0.3 v to v cc + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . diode current at any device terminal 2 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature, t stg (unprogrammed device) ?55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature, t stg (programmed device) ?40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note: all voltages referenced to v ss . the jtag fuse-blow voltage, v fb , is allowed to exceed the absolute maximum rating. the voltage is applied to the test pin when blowing the jtag fuse. recommended operating conditions min nom max units supply voltage during program execution, v cc (see note 1) msp430f11x2 1.8 3.6 v supply voltage during program execution, v cc (see note 1) msp430f11x2 msp430f12x2 1.8 3.6 v supply voltage during program/erase flash memory, v cc msp430f11x2 msp430f12x2 2.7 3.6 v supply voltage, v ss 0 v operating free-air temperature range, t a msp430f11x2 msp430f12x2 ?40 85 c lfxt1 crystal frequency, f (lfxt1) lf mode selected, xts=0 watch crystal 32 768 hz lfxt1 crystal frequency, f (lfxt1) (see note 2) xt1 selected mode, xts=1 ceramic resonator 450 8000 khz (see note 2) xt1 selected mode, xts=1 crystal 1000 8000 khz processor frequency f (system) (mclk signal) v cc = 1.8 v, msp430f11x2 msp430f12x2 dc 4.15 mhz processor frequency f (system) (mclk signal) v cc = 3.6 v, msp430f11x2 msp430f12x2 dc 8 mhz notes: 1. the lfxt1 oscillator in lf-mode requires a resistor of 5.1 m ? from xout to v ss when v cc <2.5 v. the lfxt1 oscillator in xt1-mode accepts a ceramic resonator or a crystal frequency of 4 mhz at v cc 2.2 v. the lfxt1 oscillator in xt1-mode accepts a ceramic resonator or a crystal frequency of 8 mhz at v cc 2.8 v. 2. the lfxt1 oscillator in lf-mode requires a watch crystal. the lfxt1 oscillator in xt1-mode accepts a ceramic resonator or a crystal.
slas361c ? january 2002 ? revised december 2003 17 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 4.15 mhz at 1.8 v msp430f11x2 and msp430f12x2 devices note: minimum processor frequency is defined by system clock. flash program or erase operations require a minimum v cc of 2.7 v. 9 3 2 1 0 01 2 3 4 4 v cc ? supply voltage ? v 8 mhz at 3.6 v 5 6 7 8 ? maximum processor frequency ? mhz f (system) figure 1. frequency vs supply voltage supply current (into v cc ) excluding external current parameter test conditions min typ max unit t a = ?40 c +85 c, f mclk = f (smclk) = 1 mhz, v cc = 2.2 v 200 250 a i (am) active mode f mclk = f (smclk) = 1 mhz, f(aclk) = 32,768 hz, program executes in flash v cc = 3 v 300 350 a i (am) active mode t a = ?40 c +85 c, f (mclk) = f (smclk) = f (aclk) = 4096 hz, v cc = 2.2 v 3 5 a a f (mclk) = f (smclk) = f (aclk) = 4096 hz, program executes in flash v cc = 3 v 11 18 a i (cpuoff) low-power mode, (lpm0) t a = ?40 c +85 c, f (mclk) = 0, f (smclk) = 1 mhz, v cc = 2.2 v 32 45 a i (cpuoff) low-power mode, (lpm0) a f (mclk) = 0, f (smclk) = 1 mhz, f(aclk) = 32,768 hz v cc = 3 v 55 70 a i (lpm2) low-power mode, (lpm2) t a = ?40 c +85 c, f (mclk) = f (smclk) = 0 mhz, v cc = 2.2 v 11 14 a i (lpm2) low-power mode, (lpm2) a f (mclk) = f (smclk) = 0 mhz, f(aclk) = 32,768 hz, scg0 = 0 v cc = 3 v 17 22 a t a = ?40 c 0.8 1.2 t a = 25 c v cc = 2.2 v 0.7 1 a i (lpm3) low-power mode, (lpm3) t a = 85 c v cc = 2.2 v 1.6 2.3 a i (lpm3) low-power mode, (lpm3) t a = ?40 c 1.8 2.2 t a = 25 c v cc = 3 v 1.6 1.9 a t a = 85 c v cc = 3 v 2.3 3.4 a t a = ?40 c 0.1 0.5 i (lpm4) low-power mode, (lpm4) t a = 25 c v cc = 2.2 v/3 v 0.1 0.5 a i (lpm4) low-power mode, (lpm4) t a = 85 c v cc = 2.2 v/3 v 0.8 1.9 a notes: 1. all inputs are tied to 0 v or v cc . outputs do not source or sink any current.
slas361c ? january 2002 ? revised december 2003 18 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) current consumption of active mode versus system frequency i am = i am[1 mhz] f system [mhz] current consumption of active mode versus supply voltage i am = i am[3 v] + 120 a/v (v cc ?3 v) schmitt-trigger inputs port p1 to port p3; p1.0 to p1.7, p2.0 to p2.5, p3.0 to p3.7 parameter test conditions min typ max unit v it+ positive-going input threshold voltage v cc = 2.2 v 1.1 1.5 v v it+ positive-going input threshold voltage v cc = 3 v 1.5 1.9 v v it? negative-going input threshold voltage v cc = 2.2 v 0.4 0.9 v v it? negative-going input threshold voltage v cc = 3 v 0.9 1.3 v v hys input voltage hysteresis, (v it+ ? v it? ) v cc = 2.2 v 0.3 1.1 v v hys input voltage hysteresis, (v it+ ? v it? ) v cc = 3 v 0.5 1 v standard inputs ? rst /nmi; test parameter test conditions min typ max unit v il low-level input voltage v cc = 2.2 v / 3 v v ss v ss +0.6 v v ih high-level input voltage v cc = 2.2 v / 3 v 0.8 v cc v cc v inputs px.x, tax parameter test conditions v cc min typ max unit port p1, p2: p1.x to p2.x, external trigger signal 2.2 v/3 v 1.5 cycle t (int) external interrupt timing port p1, p2: p1.x to p2.x, external trigger signa l for the interrupt flag, (see note 1) 2.2 v 62 ns t (int) external interrupt timing for the interrupt flag, (see note 1) 3 v 50 ns t (cap) timer_a, capture timing ta0, ta1, ta2 2.2 v 62 ns t (cap) timer_a, capture timing ta0, ta1, ta2 3 v 50 ns f (taext) timer_a clock frequency taclk, inclk t (h) = t (l) 2.2 v 8 mhz f (taext ) timer_a clock frequency externally applied to pin taclk, inclk t (h) = t (l) 3 v 10 mhz f (taint) timer_a clock frequency smclk or aclk signal selected 2.2 v 8 mhz f (taint) timer_a clock frequency smclk or aclk signal selected 3 v 10 mhz notes: 1. the external signal sets the interrupt flag every time the minimum t (int) cycle and time parameters are met. it may be set even with trigger signals shorter than t (int) . both the cycle and timing specifications must be met to ensure the flag is set. t (int) is measured in mclk cycles. leakage current parameter test conditions v cc min typ max unit i lkg(px.x) high-impedance leakage current port p1: p1.x, 0 7 (see notes 1 and 2) 2.2 v/3 v 50 na i lkg(px.x) high-impedance leakage current port p2: p2.x, 0 5 (see notes 1 and 2) 2.2 v/3 v 50 na notes: 1. the leakage current is measured with v ss or v cc applied to the corresponding pin(s), unless otherwise noted. 2. the leakage of the digital port pins is measured individually. the port pin must be selected for input and there must be no o ptional pullup or pulldown resistor.
slas361c ? january 2002 ? revised december 2003 19 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs port 1 to port 3; p1.0 to p1.7, p2.0 to p2.5, p3.0 to p3.7 parameter test conditions min typ max unit i (ohmax) = ?1.5 ma v cc = 2.2 v see note 1 v cc ?0.25 v cc v oh high-level output voltage i (ohmax) = ?6 ma v cc = 2.2 v see note 2 v cc ?0.6 v cc v v oh high-level output voltage i (ohmax) = ?1.5 ma v cc = 3 v see note 1 v cc ?0.25 v cc v i (ohmax) = ?6 ma v cc = 3 v see note 2 v cc ?0.6 v cc i (olmax) = 1.5 ma v cc = 2.2 v see note 1 v ss v ss +0.25 v ol low-level output voltage i (olmax) = 6 ma v cc = 2.2 v see note 2 v ss v ss +0.6 v v ol low-level output voltage i (olmax) = 1.5 ma v cc = 3 v see note 1 v ss v ss +0.25 v i (olmax) = 6 ma v cc = 3 v see note 2 v ss v ss +0.6 notes: 1. the maximum total current, i ohmax and i olmax , for all outputs combined, should not exceed 12 ma to hold the maximum voltage drop specified. 2. the maximum total current, i ohmax and i olmax , for all outputs combined, should not exceed 48 ma to hold the maximum voltage drop specified. outputs p1.x, p2.x, p3.x, tax parameter test conditions v cc min typ max unit f (p20) p2.0/aclk, c l = 20 pf 2.2 v/3 v f system f (tax) output frequency ta0, ta1, ta2, c l = 20 pf, internal clock source, smclk signal applied (see note 1) 2.2 v/3 v dc f system mhz f smclk = f lfxt1 = f xt1 40% 60% p1.4/smclk, f smclk = f lfxt1 = f lf 2.2 v/3 v 35% 65% p1.4/smclk, c l = 20 pf f smclk = f lfxt1/n 2.2 v/3 v 50%? 15 ns 50% 50%+ 15 ns t (xdc) duty cycle of o/p frequency f smclk = f dcoclk 2.2 v/3 v 50%? 15 ns 50% 50%+ 15 ns frequency p2.0/aclk, f p20 = f lfxt1 = f xt1 40% 60% p2.0/aclk, c l = 20 pf f p20 = f lfxt1 = f lf 2.2 v/3 v 30% 70% c l = 20 pf f p20 = f lfxt1/n 2.2 v/3 v 50% t (tadc) ta0, ta1, ta2, c l = 20 pf, duty cycle = 50% 2.2 v/3 v 0 50 ns notes: 1. the limits of the system clock mclk has to be met. mclk and smclk can have different frequencies.
slas361c ? january 2002 ? revised december 2003 20 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs ? ports p1, p2, and p3 (see note) figure 2 v ol ? low-level output voltage ? v 0 4 8 12 16 20 24 28 32 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 2.2 v p1.0 t a = 25 c t a = 85 c ol i ? typical low-level output current ? ma typical low-level output current vs low-level output voltage figure 3 v ol ? low-level output voltage ? v 0 10 20 30 40 50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = 3 v p1.0 t a = 25 c t a = 85 c typical low-level output current vs low-level output voltage ol i ? typical low-level output current ? ma figure 4 v oh ? high-level output voltage ? v ?28 ?24 ?20 ?16 ?12 ?8 ?4 0 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 2.2 v p1.0 t a = 25 c t a = 85 c oh i ? typical high-level output current ? ma typical high-level output current vs high-level output voltage figure 5 v oh ? high-level output voltage ? v ?60 ?50 ?40 ?30 ?20 ?10 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = 3 v p1.0 t a = 25 c t a = 85 c typical high-level output current vs high-level output voltage oh i ? typical high-level output current ? ma note: only one output is loaded at a time.
slas361c ? january 2002 ? revised december 2003 21 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) usart (see note 1) parameter test conditions min typ max unit t ( ) usart: deglitch time v cc = 2.2 v 200 430 800 ns t ( ) usart: deglitch time v cc = 3 v 150 280 500 ns notes: 1. the signal applied to the usart receive signal/terminal (urxd) should meet the timing requirements of t ( ) to ensure that the urxs flip-flop is set. the urxs flip-flop is set with negative pulses meeting the minimum-timing condition of t ( ) . the operating conditions to set the flag must be met independently from this timing constraint. the deglitch circuitry is active only on negative transi tions on the urxd line. ram parameter min nom max unit v (ramh) cpu halted (see note 1) 1.6 v notes: 1. this parameter defines the minimum supply voltage v cc when the data in the program memory ram remains unchanged. no program execution should happen during this supply voltage condition. por brownout, reset (see notes 1 and 2) parameter test conditions min typ max unit t d(bor) 2000 s v cc(start) dv cc /dt 3 v/s 0.7 v (b_it?) v v (b_it?) brownout dv cc /dt 3 v/s 1.71 v v hys(b_it?) brownout dv cc /dt 3 v/s 70 130 180 mv t (reset) pulse length needed at rst /nmi pin to accepted reset internally, v cc = 2.2 v/3 v 2 s notes: 1. the current consumption of the brown-out module is already included in the i cc current consumption data. 2. during power up, the cpu begins code execution following a period of t d(bor) after v cc = v (b_it?) + v hys(b_it?) . the default dco settings must not be changed until v cc v cc(min) . see the msp430x1xx family user?s guide for more information on the brownout circuit.
slas361c ? january 2002 ? revised december 2003 22 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) 0 1 t d(bor) v cc v (b_it?) v hys(b_it?) v cc(start) set signal for por circuitry figure 6. por/brownout reset (bor) vs supply voltage v cc(min) v cc 3 v t pw 0 0.50 1 1.50 2 0.001 1 1000 v = 3.0 v typical conditions 1ns 1ns t pw ? pulse width ? s v cc(min) ? v t pw ? pulse width ? s cc figure 7. v cc(min) level with a square voltage drop to generate a por/brownout signal v cc 0 0.50 1 1.50 2 v cc(min) t pw t pw ? pulse width ? s v cc(min) ? v 3 v 0.001 1 1000 t fall t rise t pw ? pulse width ? s t fall = t rise v = 3.0 v typical conditions cc figure 8. v cc(min) level with a triangle voltage drop to generate a por/brownout signal
slas361c ? january 2002 ? revised december 2003 23 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) crystal oscillator,lfxt1 parameter test conditions v cc min typ max unit c xin pin load xts=0; lf mode selected 2.2 v / 3 v 12 pf c xin pin load capacitance xts=1; xt1 mode selected (see note 1) 2.2 v / 3 v 2 pf c xout pin load capacitance xts=0; lf mode selected 2.2 v / 3 v 12 pf c xout pin load capacitance xts=1; xt1 mode selected (see note 1) 2.2 v / 3 v 2 pf v il input levels at xin see note 2 2.2 v / 3 v v ss 0.2 v cc v v ih input levels at xin see note 2 2.2 v / 3 v 0.8 v cc v cc v notes: 1. requires external capacitors at both terminals. values are specified by crystal manufacturers. 2. applies only when using an external logic-level clock source. not applicable when using a crystal or resonator. dco parameter test conditions v cc min typ max unit f (dco03) r sel = 0, dco = 3, mod = 0, dcor = 0, t a = 25 c 2.2 v 0.08 0.12 0.15 mhz f (dco03) r sel = 0, dco = 3, mod = 0, dcor = 0, t a = 25 c 3 v 0.08 0.13 0.16 mhz f (dco13) r sel = 1, dco = 3, mod = 0, dcor = 0, t a = 25 c 2.2 v 0.14 0.19 0.23 mhz f (dco13) r sel = 1, dco = 3, mod = 0, dcor = 0, t a = 25 c 3 v 0.14 0.18 0.22 mhz f (dco23) r sel = 2, dco = 3, mod = 0, dcor = 0, t a = 25 c 2.2 v 0.22 0.3 0.36 mhz f (dco23) r sel = 2, dco = 3, mod = 0, dcor = 0, t a = 25 c 3 v 0.22 0.28 0.34 mhz f (dco33) r sel = 3, dco = 3, mod = 0, dcor = 0, t a = 25 c 2.2 v 0.37 0.49 0.59 mhz f (dco33) r sel = 3, dco = 3, mod = 0, dcor = 0, t a = 25 c 3 v 0.37 0.47 0.56 mhz f (dco43) r sel = 4, dco = 3, mod = 0, dcor = 0, t a = 25 c 2.2 v 0.61 0.77 0.93 mhz f (dco43) r sel = 4, dco = 3, mod = 0, dcor = 0, t a = 25 c 3 v 0.61 0.75 0.9 mhz f (dco53) r sel = 5, dco = 3, mod = 0, dcor = 0, t a = 25 c 2.2 v 1 1.2 1.5 mhz f (dco53) r sel = 5, dco = 3, mod = 0, dcor = 0, t a = 25 c 3 v 1 1.3 1.5 mhz f (dco63) r sel = 6, dco = 3, mod = 0, dcor = 0, t a = 25 c 2.2 v 1.6 1.9 2.2 mhz f (dco63) r sel = 6, dco = 3, mod = 0, dcor = 0, t a = 25 c 3 v 1.69 2 2.29 mhz f (dco73) r sel = 7, dco = 3, mod = 0, dcor = 0, t a = 25 c 2.2 v 2.4 2.9 3.4 mhz f (dco73) r sel = 7, dco = 3, mod = 0, dcor = 0, t a = 25 c 3 v 2.7 3.2 3.65 mhz f (dco77) r sel = 7, dco = 7, mod = 0, dcor = 0, t a = 25 c 2.2 v 4 4.5 4.9 mhz f (dco77) r sel = 7, dco = 7, mod = 0, dcor = 0, t a = 25 c 3 v 4.4 4.9 5.4 mhz f (dco47) r sel = 4, dco = 7, mod = 0, dcor = 0, t a = 25 c 2.2 v/3 v f dco40 f dco40 f dco40 mhz f (dco47) r sel = 4, dco = 7, mod = 0, dcor = 0, t a = 25 c 2.2 v/3 v f dco40 x1.7 f dco40 x2.1 f dco40 x2.5 mhz s (rsel) s r = f rsel+1 /f rsel 2.2 v/3 v 1.35 1.65 2 ratio s (dco) s dco = f dco+1 /f dco 2.2 v/3 v 1.07 1.12 1.16 ratio d t temperature drift, r sel = 4, dco = 3, mod = 0 (see note 1) 2.2 v ?0.31 ?0.36 ?0.4 %/ c d t temperature drift, r sel = 4, dco = 3, mod = 0 (see note 1) 3 v ?0.33 ?0.38 ?0.43 %/ c d v drift with v cc variation, r sel = 4, dco = 3, mod = 0 (see note 1) 2.2 v/3 v 5 %/v notes: 1. these parameters are not production tested.
slas361c ? january 2002 ? revised december 2003 24 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) ?????? ?????? ?????? ?????? individual devices have a minimum and maximum operation frequency. the specified parameters for f dcox0 to f dcox7 are valid for all devices. the dco control bits dco0, dco1 and dco2 have a step size as defined in parameter s dco . the modulation control bits mod0 to mod4 select how often f dco+1 is used within the period of 32 dcoclk cycles. f dco is used for the remaining cycles. the frequency is an average = f dco (2 mod/32 ). all ranges selected by r sel(n) overlap with r sel(n+1) : r sel0 overlaps with r sel1 , ... r sel6 overlaps with r sel7 . wake-up from lower power modes (lpmx) parameter test conditions min typ max unit t (lpm0) v cc = 2.2 v/3 v 100 ns t (lpm2) v cc = 2.2 v/3 v 100 ns f (mclk) = 1 mhz, v cc = 2.2 v/3 v 6 t (lpm3) delay time (see note 1) f (mclk) = 2 mhz, v cc = 2.2 v/3 v 6 s t (lpm3) delay time (see note 1) f (mclk) = 3 mhz, v cc = 2.2 v/3 v 6 s f (mclk) = 1 mhz, v cc = 2.2 v/3 v 6 t (lpm4) f (mclk) = 2 mhz, v cc = 2.2 v/3 v 6 s t (lpm4) f (mclk) = 3 mhz, v cc = 2.2 v/3 v 6 s notes: 1. parameter applicable only if dcoclk is used for mclk.
slas361c ? january 2002 ? revised december 2003 25 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 10-bit adc, power supply and input range conditions (see note 1) parameter test conditions min nom max unit v cc analog supply voltage v ss = 0 v 2.2 3.6 v v (p6.x/ax) analog input voltage range (see note 2) all ax terminals. analog inputs selected in adc10ae register and pxsel.x=1 v ss v px.x/ax v cc 0 v cc v i adc10 operating supply current into v cc terminal f adc10clk = 5.0 mhz adc10on = 1, refon = 0 2.2 v 0.52 1.05 ma i adc10 into v cc terminal (see note 3) adc10on = 1, refon = 0 adc10sht0=1, adc10sht1=0, adc10div=0 3 v 0.6 1.2 ma i ref+ reference operating supply current, reference buffer disabled (see note 4) f adc10clk = 5.0 mhz adc10on = 0, refon = 1, ref2_5v = x; refout = 0 2.2v/3 v 0.25 0.4 ma i refb reference buffer operating supply current f adc10clk = 5.0 mhz adc10on = 0, adc10sr = 0 1.1 1.4 ma i refb operating supply current (see note 4) adc10on = 0, refon = 1, ref2_5v = 0 refout = 1 adc10sr = 1 0.46 0.55 ma c i ? input capacitance only one terminal can be selected at one time, px.x/ax 2.2 v 27 pf r i ? input mux on resistance 0v v ax v cc 3 v 2000 ? ? not production tested, limits verified by design notes: 1. the leakage current is defined in the leakage current table with px.x/ax parameter. 2. the analog input voltage range must be within the selected reference voltage range v r+ to v r? for valid conversion results. 3. the internal reference supply current is not included in current consumption parameter i adc10 . 4. the internal reference current is supplied via terminal v cc . consumption is independent of the adc10on control bit, unless a conversion is active. the refon bit enables the built-in reference to settle before starting an a/d conversion. 10-bit adc, external reference (see note 1) parameter test conditions min nom max unit v eref+ positive external reference voltage input v eref+ > v ref? /v eref? (see note 2) 1.4 v cc v v ref? / v eref? negative external reference voltage input v eref+ > v ref? /v eref? (see note 3) 0 1.2 v (v eref+ ? v ref?/ v eref? ) differential external reference voltage input v eref+ > v ref? /v eref? (see note 4) 1.4 v cc v i veref+ static input current 0v v eref+ v cc 2.2 v/3 v 1 a i vref?/veref? static input current 0v v eref? v cc 2.2 v/3 v 1 a notes: 1. the external reference is used during conversion to charge and discharge the capacitance array. the input capacitance, c i , is also the dynamic load for an external reference during conversion. the dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. 2. the accuracy limits the minimum positive external reference voltage. lower reference voltage levels may be applied with reduc ed accuracy requirements. 3. the accuracy limits the maximum negative external reference voltage. higher reference voltage levels may be applied with redu ced accuracy requirements. 4. the accuracy limits minimum external differential reference voltage. lower differential reference voltage levels may be appli ed with reduced accuracy requirements.
slas361c ? january 2002 ? revised december 2003 26 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 10-bit adc, built-in reference parameter test conditions min nom max unit v ref+ positive built-in reference ref2_5v = 1 for 2.5 v i vref+ i vref+ max 3 v 2.35 2.5 2.65 v v ref+ positive built-in reference voltage output ref2_5v = 0 for 1.5 v i vref+ i vref+ max 2.2 v/3 v 1.41 1.5 1.59 v v cc minimum voltage, ref2_5v = 0, i vref+ 1ma 2.2 v cc(min) v cc minimum voltage, positive built-in reference active ref2_5v = 1, i vref+ 0.5ma v ref+ + 0.15 v v cc(min) positive built-in reference active ref2_5v = 1, i vref+ 1ma v ref+ + 0.15 v i vref+ load current out of v ref+ 2.2 v 0.5 ma i vref+ load current out of v ref+ terminal 3 v 1 ma i vref+ = 500 a +/? 100 a analog input voltage ~0.75 v; 2.2 v 2 lsb i l(vref)+ ? load-current regulation vref+ analog input voltage ~0.75 v; ref2_5v = 0 3 v 2 lsb i l(vref)+ ? load-current regulation v ref+ terminal i vref+ = 500 a 100 a analog input voltage ~1.25 v; ref2_5v = 1 3 v 2 lsb t dl(vref) + ? load current regulation i vref+ =100 a 900 a, v cc =3 v, ax ~0.5 x v ref+ adc10sr = 0 400 ns t dl(vref) + ? load current regulation v ref+ terminal vref+ v cc =3 v, ax ~0.5 x v ref+ error of conversion result 1 lsb adc10sr = 1 2000 ns c vref+ capacitance at pin v ref+ (see note 1) refon =1, i vref+ ? 1 ma 2.2 v/3 v 100 pf t ref+ ? temperature coefficient of built-in reference i vref+ is a constant in the range of 0 ma i vref+ 1 ma 2.2 v/3 v 100 ppm/ c t ? settle time of internal reference voltage and i vref+ = 0.5 ma,v ref+ = 1.5 v, v cc = 3.6 v, refon = 0 1 30 s t refon ? reference voltage and v ref+ (see note 2) i vref+ = 0.5 ma, v ref+ = 1.5 v, adc10sr = 0 0.8 s v ref+ (see note 2) i vref+ = 0.5 ma, v ref+ = 1.5 v, v cc = 2.2 v, refon = 1 adc10sr = 1 2.5 ? not production tested, limits characterized ? not production tested, limits verified by design notes: 1. the capacitance applied to the internal buf fer operational amplifier, if switched to terminal p2.4/t a2/a4/v ref+ /v eref+ (refout=1), must be limited; the reference buffer may become unstable otherwise. notes: 2. the condition is that the error in a conversion started after t refon is less than 0.5 lsb.
slas361c ? january 2002 ? revised december 2003 27 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 10-bit adc, timing parameters parameter test conditions min nom max unit f adc10clk error of conversion result ? 1 adc10sr = 0 0.450 6.3 mhz f adc10clk error of conversion result ? 1 lsb adc10sr = 1 0.450 1.5 mhz f adc10osc adc10div=0, f adc10clk =f adc10osc 2.2 v/ 3v 3.7 6.3 mhz t convert conversion time internal oscillator, f adc10osc = 3.7 mhz to 6.3 mhz 2.2 v/ 3 v 2.06 3.51 s t convert conversion time external f adc10clk from aclk, mclk or smclk: adc10ssel 0 13 adc10div 1/f adc10clk s t adc10on ? turn on settling time of the adc (see note 1) 100 ns t sample ? sampling time r s = 400 ? , r i = 2000 , 3 v 1400 ns t sample ? sampling time r s = 400 ? , r i = 2000 ? , c i = 20 pf (see note 2) 2.2 v 1400 ns ? not production tested, limits characterized ? not production tested, limits verified by design notes: 1. the condition is that the error in a conversion started after t adc10on is less than 0.5 lsb. the reference and input signal are already settled. 2. approximately eight tau ( ) are needed to get an error of less than 0.5 lsb. t sample = ln(2 n+1 ) x (r s + r i ) x c i + 800 ns. (adc10sr = 0, n = adc resolution = 10, r s = external source resistance) t sample = ln(2 n+1 ) x (r s + r i ) x c i + 2.5 s. (adc10sr = 1, n = adc resolution = 10, r s = external source resistance) 10-bit adc, linearity parameters parameter test conditions min nom max unit e i integral linearity error 1.4 v (v eref+ ? v ref? /v eref? ) min 1.6 v 2.2 v/3 v 1 lsb e i integral linearity erro r 1.6 v < (v eref+ ? v ref? /v eref? ) min [v cc ] 2.2 v/3 v 1 lsb e d differential linearity error (v eref+ ? v ref? /v eref? ) min (v eref+ ? v ref? /v eref? ) 2.2 v/3 v 1 lsb e o offset error (v eref+ ? v ref? /v eref? ) min (v eref+ ? v ref? /v eref? ), internal impedance of source r s < 100 ? , 2.2 v/3 v 2 4 lsb e g gain error (v eref+ ? v ref? /v eref? ) min (v eref+ ? v ref? /v eref? ), 2.2 v/3 v 1.1 2 lsb e t total unadjusted error (v eref+ ? v ref? /v eref? ) min (v eref+ ? v ref? /v eref? ), 2.2 v/3 v 2 5 lsb
slas361c ? january 2002 ? revised december 2003 28 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) 10-bit adc, temperature sensor and built-in v mid parameter test conditions min nom max unit i sensor operating supply current into refon = 0, inch = 0ah, 2.2 v 40 120 a i sensor operating supply current into v cc terminal (see note 1) refon = 0, inch = 0ah, adc10on=na, t a = 25 c 3 v 60 160 a v sensor ? adc10on = 1, inch = 0ah, 2.2 v 986 986 5% mv v sensor ? adc10on = 1, inch = 0ah, t a = 0 c 3 v 986 986 5% mv tc sensor ? adc10on = 1, inch = 0ah 2.2 v 3.55 3.55 3% mv/ c tc sensor ? adc10on = 1, inch = 0ah 3 v 3.55 3.55 3% mv/ c t sensor(sample) ? sample time required if channel adc10on = 1, inch = 0ah, 2.2 v 30 s t sensor(sample) ? sample time required if channel 10 is selected (see note 2) adc10on = 1, inch = 0ah, error of conversion result 1 lsb 3 v 30 s i vmid current into divider at channel 11 adc10on = 1, inch = 0bh, 2.2 v na a i vmid current into divider at channel 11 (see note 3) adc10on = 1, inch = 0bh, 3 v na a v mid v cc divider at channel 11 adc10on = 1, inch = 0bh, 2.2 v 1.1 1.1 0.04 v v mid v cc divider at channel 11 adc10on = 1, inch = 0bh, v mid is ~0.5 x v cc 3 v 1.5 1.50 0.04 v t vmid(sample) sample time required if channel adc10on = 1, inch = 0bh, 2.2 v 1400 ns t vmid(sample) sample time required if channel 11 is selected (see note 4) adc10on = 1, inch = 0bh, error of conversion result 1 lsb 3 v 1220 ns ? not production tested, limits characterized notes: 1. the sensor current i sensor is consumed if (adc10on = 1 and refon = 1), or (adc10on=1 and inch=0ah and sample signal is high). therefore it includes the constant current through the sensor and the reference. 2. the typical equivalent impedance of the sensor is 51 k ? . the sample time required includes the sensor-on time t sensor(on) . 3. no additional current is needed. the v mid is used during sampling. 4. the on-time t vmid(on) is included in the sampling time t vmid(sample) ; no additional on time is needed.
slas361c ? january 2002 ? revised december 2003 29 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued) flash memory parameter test conditions v cc min nom max unit v cc(pgm/ erase) program and erase supply voltage 2.7 3.6 v f ftg flash timing generator frequency 257 476 khz i pgm supply current from v cc during program 2.7 v/ 3.6 v 3 5 ma i erase supply current from v cc during erase 2.7 v/ 3.6 v 3 7 ma t cpt cumulative program time see note 1 2.7 v/ 3.6 v 4 ms t cmerase cumulative mass erase time see note 2 2.7 v/ 3.6 v 200 ms program/erase endurance 10 4 10 5 cycles t retention data retention duration t j = 25 c 100 years t word word or byte program time 35 t block, 0 block program time for 1 st byte or word 30 t block, 1-63 block program time for each additional byte or word see note 3 21 t ftg t block, end block program end-sequence wait time see note 3 6 t ftg t mass erase mass erase time 5297 t seg erase segment erase time 4819 notes: 1. the cumulative program time must not be exceeded during a block-write operation. this parameter is only relevant if the block write feature is used. 2. the mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/f ftg ,max = 5297x1/476khz). to achieve the required cumulative mass erase time the flash controller?s mass erase operation can be repeated until this time is met. (a worst case minimum of 19 cycles are required). 3. these values are hardwired into the flash controller?s state machine; t ftg = 1/f ftg . jtag interface parameter test conditions v cc min nom max unit f tck tck input frequency see note 1 2.2 v 0 5 mhz f tck tck input frequency see note 1 3 v 0 10 mhz r internal internal pull-up resistance on tms, tck, tdi/tclk see note 2 2.2 v/ 3 v 25 60 90 k ? notes: 1. f tck may be restricted to meet the timing requirements of the module selected. 2. tms, tdi/tclk, and tck pull-up resistors are implemented in all flash versions. jtag fuse (see note 1) parameter test conditions v cc min nom max unit v cc(fb) supply voltage during fuse-blow condition t a = 25 c 2.5 v v fb voltage level on test for fuse-blow 6 7 v i fb supply current into test during fuse blow 100 ma t fb time to blow fuse 1 ms notes: 1. once the fuse is blown, no further access to the msp430 jt ag/t est and emulation features is possible. the jtag block is switched to bypass mode.
slas361c ? january 2002 ? revised december 2003 30 post office box 655303 ? dallas, texas 75265 application information input/output schematic port p1, p1.0 to p1.3, input/output with schmitt-trigger en d p1.0/taclk/adc10clk p1.1/ta0 p1.2/ta1 p1.3/ta2 0 1 0 1 interrupt edge select en set q p1ie.x p1ifg.x p1irq.x interrupt flag p1ies.x p1sel.x module x in p1in.x p1out.x module x out direction control from module p1dir.x p1sel.x pad logic note: x = bit/identifier, 0 to 3 for port p1 pnsel.x pndir.x direction control from module pnout.x module x out pnin.x module x in pnie.x pnifg.x pnies.x p1sel.0 p1dir.0 p1dir.0 p1out.0 adc10clk p1in.0 taclk ? p1ie.0 p1ifg.0 p1ies.0 p1sel.1 p1dir.1 p1dir.1 p1out.1 out0 signal ? p1in.1 cci0a ? p1ie.1 p1ifg.1 p1ies.1 p1sel.2 p1dir.2 p1dir.2 p1out.2 out1 signal ? p1in.2 cci1a ? p1ie.2 p1ifg.2 p1ies.2 p1sel.3 p1dir.3 p1dir.3 p1out.3 out2 signal ? p1in.3 cci2a ? p1ie.3 p1ifg.3 p1ies.3 ? signal from or to timer_a
slas361c ? january 2002 ? revised december 2003 31 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p1, p1.4 to p1.7, input/output with schmitt-trigger and in-system access features en d p1.4?p1.7 0 1 0 1 interrupt edge select en set q p1ie.x p1ifg.x p1irq.x interrupt flag p1ies.x p1sel.x module x in p1in.x p1out.x module x out direction control from module p1dir.x p1sel.x pad logic bus keeper 60 k ? control by jtag 0 1 tdo controlled by jtag p1.x tdi p1.x tst tms tst tck tst controlled by jtag tst p1.x p1.x note: the test pin should be protected from potential emi and esd voltage spikes. this may require a smaller external pulldown resistor in some applications. x = bit identifier, 4 to 7 for port p1 during programming activity and during blowing the fuse, the pin tdo/tdi is used to apply the test input for jtag circuitry. p1.7/ta2/tdo/tdi p1.6/ta1/tdi/tclk p1.5/ta0/tms p1.4/smclk/tck typical test bum and test fuse dv cc pnsel.x pndir.x direction control from module pnout.x module x out pnin.x module x in pnie.x pnifg.x pnies.x p1sel.4 p1dir.4 p1dir.4 p1out.4 smclk p1in.4 unused p1ie.4 p1ifg.4 p1ies.4 p1sel.5 p1dir.5 p1dir.5 p1out.5 out0 signal ? p1in.5 unused p1ie.5 p1ifg.5 p1ies.5 p1sel.6 p1dir.6 p1dir.6 p1out.6 out1 signal ? p1in.6 unused p1ie.6 p1ifg.6 p1ies.6 p1sel.7 p1dir.7 p1dir.7 p1out.7 out2 signal ? p1in.7 unused p1ie.7 p1ifg.7 p1ies.7 ? signal from or to timer_a
slas361c ? january 2002 ? revised december 2003 32 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p2, p2.0 to p2.2, input/output with schmitt-trigger p2out. x module x out p2dir.x direction control from module p2sel.x d en interrupt edge select p2ies.x p2sel.x p2ie.x p2ifg.x p2irq.x en set q 0 1 1 0 to adc10, p2.0/aclk/a0 p2.1/inclk/a1 p2.2/ta0/a2 module x in p2in.x a0, or a1, or a2 selected in adc10 pad logic 0: input 1: output bus keeper adc10ae.x note: 0 x 2 a0, or a1, or a2 pnsel.x pndir.x direction control from module pnout.x module x out pnin.x module x in pnie.x pnifg.x pnies.x p2sel.0 p2dir.0 p2dir.0 p2out.0 aclk ? p2in.0 unused p2ie.0 p2ifg.0 p1ies.0 p2sel.1 p2dir.1 p2dir.1 p2out.1 v ss p2in.1 inclk ? p2ie.1 p2ifg.1 p1ies.1 p2sel.2 p2dir.2 p2dir.2 p2out.2 out0 signal ? p2in.2 cci0b ? p2ie.2 p2ifg.2 p1ies.2 ? timer_a
slas361c ? january 2002 ? revised december 2003 33 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p2, p2.3 to p2.4, input/output with schmitt-trigger p2out.4 module x out p2dir.4 p2sel.4 d en interrupt edge select p2ies.4 p2sel.4 p2ie.4 p2ifg.4 p2irq.07 en set q 0 1 1 0 to adc10, a4 p2.4/ unused p2in.4 a4 selected pad logic 0: input 1: output bus keeper adc10ae.4 p2dir.4 ta2/ a4/ v ref+ p2out.3 module x out p2dir.3 p2sel.3 d en interrupt edge select p2ies.x p2sel.x p2ie.4 p2ifg.4 p2irq.07 en set q 0 1 1 0 to adc10, a3 p2.3/ module x in p2in.4 a3 selected pad logic 0: input 1: output bus keeper adc10ae.3 p2dir.3 ta1/ a3/ v ref? _ + reference circuit in adc10 module on on typ. 1.25 v a10 on refon ref_x av cc out ref+ 2_5 v av cc v + r av ss v ? r 01 sref adc10 ctl0.12..14) sref.2 adc10 ctl0.14) 0,4 1,5 0 /v eref? v eref+ /
slas361c ? january 2002 ? revised december 2003 34 post office box 655303 ? dallas, texas 75265 application information port p2, p2.3 to p2.4, input/output with schmitt-trigger (continued) pnsel.x pndir.x direction control from module pnout.x module x out pnin.x module x in pnie.x pnifg.x pnies.x p2sel.3 p2dir.3 p2dir.3 p2out.3 out1 signal ? p2in.3 cci1b ? p2ie.3 p2ifg.3 p1ies.3 p2sel.4 p2dir.4 p2dir.4 p2out.4 out2 signal ? p2in.4 unused p2ie.4 p2ifg.4 p1ies.4 ? timer_a input/output schematic (continued) port p2, p2.5, input/output with schmitt-trigger and r osc function for the basic clock module en d p2.5/r osc 0 1 0 1 interrupt edge select en set q p2ie.5 p2ifg.5 p2irq.5 interrupt flag p2ies.5 p2sel.5 module x in p2in.5 p2out.5 module x out direction control from module p2dir.5 p2sel.5 pad logic note: dcor: control bit from basic clock module: if it is set p2.5 is disconnected from p2.5 pad. bus keeper 0 1 0 1 v cc internal to basic clock module dcor dc generator 0: input 1: output pnsel.x pndir.x direction control from module pnout.x module x out pnin.x module x in pnie.x pnifg.x pnies.x p2sel.5 p2dir.5 p2dir.5 p2out.5 v ss p2in.5 unused p2ie.5 p2ifg.5 p2ies.5
slas361c ? january 2002 ? revised december 2003 35 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p2, unbonded bits p2.6 and p2.7 en d 0 1 0 1 interrupt edge select en set q p2ie.x p2ifg.x p2irq.x interrupt flag p2ies.x p2sel.x module x in p2in.x p2out.x module x out direction control from module p2dir.x p2sel.x bus keeper 0 1 0: input 1: output node is reset with puc puc note: x = bit/identifier, 6 to 7 for port p2 without external pins p2sel.x p2dir.x direction control from module p2out.x module x out p2in.x module x in p2ie.x p2ifg.x p2ies.x p2sel.6 p2dir.6 p2dir.6 p2out.6 v ss p2in.6 unused p2ie.6 p2ifg.6 p2ies.6 p2sel.7 p2dir.7 p2dir.7 p2out.7 v ss p2in.7 unused p2ie.7 p2ifg.7 p2ies.7 note: unbonded bits 6 and 7 of port p2 can be used as interrupt flags. only software can affect the interrupt flags. they work a s software interrupts.
slas361c ? january 2002 ? revised december 2003 36 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p3, p3.0, p3.6 and p3.7 input/output with schmitt-trigger p3out.x module x out p3dir.x direction control from module p3sel.x d en 0 1 1 0 to adc10 p3.0/ste0/a5 p3.6/a6 p3.7/a7 module x in p3in.x a5, or a6, or a7 selected in adc10 pad logic 0: input 1: output bus keeper adc10ae.x note: x (0,6,7) a5, or a6, or a7 pnsel.x pndir.x direction control from module pnout.x module x out pnin.x module x in p3sel.0 p3dir.0 v ss p3out.0 v ss p3in.0 ste0 ? p3sel.6 p3dir.1 p3dir.6 p3out.6 v ss p3in.6 unused p3sel.7 p3dir.2 p3dir.7 p3out.7 v ss p3in.7 unused ? usart0
slas361c ? january 2002 ? revised december 2003 37 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p3, p3.1 input/output with schmitt-trigger p3.1/simo0 p3in.1 pad logic en d p3out1 p3dir.1 p3sel.1 (si)mo0 0 1 0 1 dcm_simo sync mm ste stc from usart0 si(mo)0 to usart0 0: input 1: output port p3, p3.2, input/output with schmitt-trigger p3.2/somi0 p3in.2 pad logic en d p3out.2 p3dir.2 p3sel.2 0 1 0 1 dcm_somi sync mm ste stc so(mi)0 from usart0 (so)mi0 to usart0 0: input 1: output
slas361c ? january 2002 ? revised december 2003 38 post office box 655303 ? dallas, texas 75265 application information input/output schematic (continued) port p3, p3.3, input/output with schmitt-trigger p3.3/uclk0 p3in.3 pad logic en d p3out.3 p3dir.3 p3sel.3 uclk.0 0 1 0 1 dcm_uclk sync mm ste stc from usart0 uclk0 to usart0 0: input 1: output note: uart mode: the uar t clock can only be an input. if uart mode and uart function are selected, the p3.3/uclk0 is always an input. spi, slave mode: the clock applied to uclk0 is used to shift data in and out. spi, master mode: the clock to shift data in and out is supplied to connected devices on pin p3.3/uclk0 (in slave mode). port p3, p3.4, and p3.5 input/output with schmitt-trigger p3in.x module x in pad logic en d p3out.x p3dir.x p3sel.x module x out direction control from module 0 1 0 1 p3.4/utxd0 p3.5/urxd0 0: input 1: output x {4,5} pnsel.x pndir.x direction control from module pnout.x module x out pnin.x module x in p3sel.4 p3dir.4 v cc p3out.4 utxd0 ? p3in.4 unused p3sel.5 p3dir.5 v ss p3out.5 v ss p3in.5 urxd0 ? ? output from usart0 module ? input to usart0 module
slas361c ? january 2002 ? revised december 2003 39 post office box 655303 ? dallas, texas 75265 application information jtag fuse check mode msp430 devices that have the fuse on the test terminal have a fuse check mode that tests the continuity of the fuse the first time the jtag port is accessed after a power-on reset (por). when activated, a fuse check current, i tf , of 1 ma at 3 v, 2.5 ma at 5 v can flow from the test pin to ground if the fuse is not burned. care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. when the test pin is taken back low after a test or programming session, the fuse check mode and sense currents are terminated. activation of the fuse check mode occurs with the first negative edge on the tms pin after power up or if tms is being held low during power up. the second positive edge on the tms pin deactivates the fuse check mode. after deactivation, the fuse check mode remains inactive until another por occurs. after each por the fuse check mode has the potential to be activated. the fuse check current will only flow when the fuse check mode is active and the tms pin is in a low state (see figure 10). therefore, the additional current flow can be prevented by holding the tms pin high (default condition). time tms goes low after por tms i tf i test figure 10. fuse check mode current, msp430f11x2, msp430f12x2 the jtag pins are terminated internally, and therefore do not require external termination. note: the code and ram data protection is ensured if the jtag fuse is blown and the 256-bit bootloader access key is used. also, see the bootstrap loader section for more information.
slas361c ? january 2002 ? revised december 2003 40 post office box 655303 ? dallas, texas 75265 mechanical data dw (r-pdso-g**) plastic small-outline package 16 pins shown 4040000 / d 01/00 seating plane 0.400 (10,15) 0.419 (10,65) 0.104 (2,65) max 1 0.012 (0,30) 0.004 (0,10) a 8 16 0.020 (0,51) 0.014 (0,35) 0.291 (7,39) 0.299 (7,59) 9 0.010 (0,25) 0.050 (1,27) 0.016 (0,40) (15,24) (15,49) pins ** 0.010 (0,25) nom a max dim a min gage plane 20 0.500 (12,70) (12,95) 0.510 (10,16) (10,41) 0.400 0.410 16 0.600 24 0.610 (17,78) 28 0.700 (18,03) 0.710 0.004 (0,10) m 0.010 (0,25) 0.050 (1,27) 0 ? 8 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). d. falls within jedec ms-013
slas361c ? january 2002 ? revised december 2003 41 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 ? 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
slas361c ? january 2002 ? revised december 2003 42 post office box 655303 ? dallas, texas 75265 rhb (s?pqfp?n32) plastic quad flatpack ????? ????? ????? ????? ????? notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. qfn (quad flatpack no?lead) package configuration. d. the package thermal performance may be enhanced by bonding the thermal die pad to an external thermal plane. this pad is electrically and thermally connected to the backside of the die and possibly selected ground leads. e. falls within jedec mo?220.

mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
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